1. Field of the Invention
The present invention relates to plasma etch methods for forming patterned silicon nitride layers within integrated circuits. More particularly, the present invention relates to a plasma etch method for forming a patterned silicon nitride layer substantially free of plasma etch bias within an integrated circuit.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
It is common within the method for forming integrated circuits within and upon semiconductor substrates to employ patterned silicon nitride layers at several locations within those integrated circuits when forming those integrated circuits. In particular, patterned silicon nitride layers are most typically employed within integrated circuits as thermal oxidation masking layers within a local oxidation of silicon (LOCOS) thermal oxidation method through which portions of a silicon semiconductor substrate are thermally oxidized to form field oxide (FOX) isolation regions within and upon the silicon semiconductor substrate. To a lesser extent, patterned silicon nitride layers are also known in the art of integrated circuit fabrication to be employed as dielectric layers and adhesion promoter layers separating patterned conductor layers within integrated circuits.
While the use of patterned silicon nitride layers within integrated circuits has become common in the art of integrated circuit fabrication, the use of patterned silicon nitride layers within advanced integrated circuits of linewidth and pitch dimensions less than about 0.5 microns is not entirely without problems. In particular, there exist several problems when forming through plasma etch methods patterned silicon nitride layers of linewidth and pitch dimensions less than about 0.5 microns when those patterned silicon nitride layers are employed in forming thermal oxidation masking layers within a local oxidation of silicon (LOCOS) method through which portions of a silicon semiconductor substrate are oxidized to form field oxide (FOX) isolation regions within and upon the silicon semiconductor substrate. The problems include, but are not limited to: (1) the presence of a plasma etch bias of the patterned silicon nitride layer with respect to a patterned photoresist layer which is employed as an etch mask layer in forming the patterned silicon nitride layer from a blanket silicon nitride layer through the plasma etch method; (2) the presence of undesirable etching into a pad oxide layer and undesirable damage to a semiconductor substrate formed beneath the patterned silicon nitride layer when a blanket silicon nitride layer is over-etched through the plasma etch method employed in forming the patterned silicon nitride layer; and (3) the presence of pattern dimension non-uniformity for patterned silicon nitride layers formed upon larger diameter semiconductor substrates. It is towards providing a plasma etch method for forming upon semiconductor substrates for use within integrated circuits patterned silicon nitride layers of linewidth and pitch less than about 0.5 microns absent problems of the foregoing type that the present invention is generally directed.
Plasma etch methods and etchant gas compositions through which blanket silicon nitride layers may be etched to form patterned silicon nitride layers are known in the art of integrated circuit fabrication. For example, Wolf et al., Silicon Processing for the VLSI Era, Vol. 1: Process Technology, Lattice Press (Sunset Beach, Calif.; 1986), pg. 581, discloses, in general, several etchant gas compositions which may be employed within plasma etch methods through which patterned silicon nitride layers may be formed within integrated circuits. In addition, Clark, in U.S. Pat. No. 4,180,432 discloses plasma etch etchant gas compositions comprising comparatively low concentrations (ie: about 5-15 volume percent) of carbon tetrafluoride in oxygen, which plasma etch etchant gas compositions exhibit within integrated circuits favorable etch rates for silicon oxide layers with respect to both silicon nitride layers and silicon substrates. Finally, Jacob, in U.S. Pat. No. Re. 30,505 discloses etchant gas compositions preferably consisting essentially of binary mixtures of oxygen and halocarbons of no greater than two carbon atoms, where at least one of the carbon atoms within the halocarbon is linked to a predominance of fluorine atoms and where the halocarbons are preferably present at comparatively high concentrations (ie: about 75-99 volume percent) within the binary mixtures. The method provides for efficient plasma etch bias free plasma etching of various insulator and conductor layers within integrated circuits to form patterned insulator and conductor layers of linewidth and pitch dimensions as low as about of 4 microns (ie: 0.15 mils).
While the teachings of Jacob bear some relevance to the problems towards which the method of the present invention is directed, Jacob neither discloses: (1) patterned silicon nitride layers employed as masking layers within thermal oxidation masks for forming field oxide (FOX) isolation regions within and upon semiconductor substrates through local oxidation of silicon (LOCOS) methods within integrated circuits; nor discloses (2) the particular problems associated with forming patterned silicon nitride layers substantially free of plasma etch bias at linewidth and pitch dimensions of less than about 0.5 microns. Substantially plasma etch bias free patterned silicon nitride layers of linewidth and pitch dimensions less than about 0.5 microns are desirable within advanced integrated circuits since plasma etch bias is often a significant portion of linewidth and pitch dimension of patterned layers within advanced integrated circuits. Further, such plasma etch bias is often encountered within integrated circuits under circumstances where it is not readily compensated.
Thus, it is desirable to provide within the art of integrated circuit fabrication plasma etch methods and materials through which there may be formed from blanket silicon nitride layers patterned silicon nitride layers of linewidth and pitch dimensions less than about 0.5 microns substantially free of plasma etch bias. Particularly desirable are plasma etch methods and materials which provide patterned silicon nitride layers in accord with the foregoing characteristics, where the patterned silicon nitride layers are employed within thermal oxidation mask layers for forming field oxide (FOX) isolation regions within those integrated circuits while avoiding damage to silicon oxide pad oxide layers and semiconductor substrates formed beneath the patterned silicon nitride insulator layers. It is towards these goals that the present invention is specifically directed.